The present invention relates to an integrating analog to digital converter having offset error compensation.
A conventional integrating analog to digital converter (referred to as an A/D converter) will first be described with reference to FIGS. 1 and 2. A dual-slope A/D converter is illustrated, by way of block diagram, in FIG. 1. A waveform of an integration output signal, which is useful in explaining the operation of the converter is illustrated in FIG. 2. As shown, an analog input voltage V.sub.IN to be converted into a digital form and a reference voltage -V.sub.R of opposite polarity to the voltage of V.sub.IN are inputted into a switch circuit 2. The switch circuit 2 selectively provides the input voltages V.sub.IN and the reference voltage -V.sub.R to an integration circuit 6, under control of a control circuit 4. The integration circuit 6 includes an integration resistor 8, an integration capacitor 10 and an operational amplifier 12. The operational amplifier 12 is grounded at the non-inverted input terminal (+) and is connected at the inverted input terminal (-) to the integration resistor 8. The output voltage from the integration circuit 6 is applied to one input terminal of a comparator 14 and is compared with a threshold voltage Vc provided to the other input terminal of the comparator 14. The comparator 14 produces an output signal of HIGH or LOW level in accordance with the result of the comparison and the output signal is supplied to the control circuit 4. Upon receipt of a start signal SP and the comparison signal, the control circuit 4 produces a counter control signal to a counter circuit 16. In response to the counter control signal, the counter circuit 16 sequentially counts clock pulses CP supplied thereto. The counter output signal is applied to the control circuit 4 and finally is produced in digital form from the counter circuit 16. Upon receipt of the counter output signal, the control circuit 4 supplies a switch control signal to a switch circuit 2 and finally produces an A/D conversion end signal EP.
In such an A/D converter, the switch circuit 2 first selects the analog input voltage V.sub.IN during a time period T1 previously set and which in turn is integrated by the integration circuit 6. Following the time period T1, the switch circuit 2 selects the reference voltage -V.sub.R and which in turn is integrated by the integration circuit 6. During a time period T2 until the output signal from the integration circuit 6 reaches the threshold voltage Vc, clock pulses CP are counted by the counter circuit 16. At this time, the analog input voltage V.sub.IN and the reference voltage -V.sub.R are expressed by the following equation EQU V.sub.IN =T2/T1.times.V.sub.R ( 1)
As seen from the equation (1), if the given time period T1 and the reference voltage -V.sub.R are previously known, an unknown analog voltage V.sub.IN may be calculated by measuring the second integration period T2. In fact, however, an operational amplifier 12 in the integration circuit 6 has an offset voltage and hence the digital amount expressed by the equation (1) includes an error. When the offset voltage Vos is taken into consideration, the equation (1) is rewritten EQU V.sub.IN =T2/T1.times.V.sub.R -T2/T1.times.Vos-Vos (2)
The second and third terms in the equation (2) indicate an error caused by the offset voltage Vos.
In the conventional circuit, an additional means for compensating for the offset voltage Vos is used in order that the offset voltage Vos does not adversely affect the conversion accuracy. For example, the offset voltage is manually adjusted to be zero every A/D conversion. In another example, the offset voltage Vos is applied to a capacitor which is additionally provided for charging it. At the integration time, the offset voltage Vos is superposed on the analog input voltage V.sub.IN and the reference voltage -V.sub.R thereby to eliminate the effect of the offset voltage Vos.
The first method by manual operation is disadvantageous when the A/D converter is fabricated as an integrated circuit. The second method is also disadvantageous in that the capacitance must be at least approximately 0.1 (.mu.F). Accordingly, in fabricating the circuit, the capacitor must be externally attached to the circuit with the result that the number of parts increases which increases the manufacturing cost.